"粽"要职位等你来看！
采用5nm制程！
· 此次合作将恩智浦优质汽车产品和功能安全与台积电业界领先的5纳米制程相结合，进一步推动汽车向强大的道路计算系统转变。
· 恩智浦面向汽车领域的突破性SoC平台旨在以功能安全、网络安全和数据完整性为重点，简化和加速车辆架构快速创新。
基于双方在16纳米制程合作的多个成功设计，恩智浦与台积电扩大合作范围，针对新一代汽车处理器打造5纳米系统单芯片（SoC）平台。通过合作，恩智浦产品将解决多种功能和工作负载需求，包含联网座舱、高性能域控制器、自动驾驶、高级汽车网络、混合推进控制与整合底盘管理等。
作为全球领先的汽车半导体供应商，恩智浦在车辆控制、汽车安全、车载娱乐与数字仪表板方面拥有丰富经验。恩智浦的5纳米研发基于已构建的S32架构，兼具可扩展性和通用软件环境，进一步简化并大幅提升软件性能，满足未来汽车需求。恩智浦将运用5纳米技术的运算能力和功耗效率，满足先进汽车架构对高度整合、电源管理和运算能力的需求，同时运用其知名IP组合应对严格的功能安全与信息安全要求。
台积电的5纳米技术是目前全球领先的量产制程工艺。恩智浦将采用台积电5纳米强效版制程（N5P），与前一代7纳米制程相较，其速度提升约20%，功耗降低约40%，同时拥有业界全面的设计生态系统的支持。
相关热招职位
IP Verification EngineerLocation: Shanghai(上下滑动启阅)
Responsibilities:
•You will be responsible for digital IP and subsystem level verification.
•Create verification plans with designers.
•Develop DV architecture and verification environment.
•Verification execution and sign-off.
•Interface to HW and SW design teams, as well as to architecture and system engineering teams, to understand functionality and application of the IP subsystem / SoC / system.
Requirements:
• Bachelor degree or above with EE (Master is preferred), Communication or Automation related major.
• Solid background with ASIC design verification flow and multiple ASIC tape out experience.
• Complex IP/ASIC/SOC design verification background, direct experience in IP/SOC or Industry bus standard (Display, HDMI, DP, MIPI or high speed IO interface).
• Familiar with SystemVerilog/UVM for testbench creation, debug, reuse, constrained-random stimulus and functional coverage.
• Solid knowledge on SystemVerilog, C/C++, Verilog.
• Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA).
• Good communication skills and team work.
• Good oral and written English skills.
请将简历投递至：talent@nxp.com
邮件注明：姓名+申请职位+工作城市
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