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恩智浦是嵌入式控制器领域的领先供应商，在工业和消费电子市场都拥有深厚的根基。我们在8位、16位和32位平台上拥有广泛的MCU产品组合，具有领先的低功耗、模拟、控制和通信IP功能。产品组合可支持网络、汽车、消费电子和工业等诸多领域的应用。
(下文含热招职位信息)
比如，近日恩智浦展示了应用于MCU的Glow神经网络编译器为基于视觉和语音的机器学习应用带来的诸多优势。
(点击上图了解更多讯息)
恩智浦是首家针对MCU实现相较于标准版Glow 2至3倍性能的半导体供应商。
开源Glow编译器最初由Facebook开发，恩智浦现在将其集成到eIQ™机器学习软件开发环境中，为旗下i.MX RT系列跨界MCU提供高性能推理。
恩智浦的Glow实施面向Arm Cortex-M内核和Cadence Tensilica HiFi 4 DSP，为i.MX RT系列跨界MCU提供特定平台的优化。
目前相关SoC社招职位正在招募中
↓ 如果你适合如下职位 ↓
请将简历投递至：talent@nxp.com
邮件注明：姓名+申请职位+工作城市
Director of SoC Integration
Location: Shanghai
(上下滑动启阅)
Responsibilities:
- Fully own the Design, DFT, Verification for Subsystems/SOCs from Initial specification till Tape out and beyond.
- Supervising RTL/DFT/Verification Sign off, timing constraints, CDC and work with different functions like verification, synthesis, etc. to get to a production quality Silicon.
- Leading various aspects of Test architecture including Scan & ATPG, Memory BIST, Logic BIST, Analog/PHY test and post-silicon support with test pattern generation.
- Manage, build and develop teams of fresh and experienced engineers. Train and mentor fresh engineers for increased productivity.
- Build up strong collaboration with other R&D teams like Architecture, SoC Implementation, DIG IP, Mixed-Signal IP, Design Enablement, Packaging, Board design and Validation to achieve all project milestones.
- Influences technical strategy to drive innovation, e.g., products, technology and/or patents) that consistently contributes to significant revenue and profit.
- Directs and controls the activities of a broad functional area through several department managers within the company.
- Responsible for people development, goal setting and team performance.
- Developing project plans including resource, schedules, progress reports, verification plans, signoff checklists and tracking milestones.
- Holding periodic internal and external reviews to ensure quality and meet delivery criteria.
- Working with various EDA vendors to deploy next gen design technologies.
- Ensure quality adherence during all stages of the project life cycle. Also carry out a thorough analysis of existing processes and recommend and implement the process improvements to ensure ‘Zero Defect’ chips.
- Ensure that SMART metrics are established to measure the processes and goals.
Requirements:
- Bachelor degree or above, major in Electronic Engineering/Computer Science or other related discipline.
- Minimum 15 years’ relevant working experience in Semiconductor industry.
- Candidate should be an experienced manager leading a team in SoC integration, verification, and DFT.
- Experience with various emulation/accelerator methods and use-case environments is an additional benefit.
- Experience of SoCs based on ARM A/R/M Multi Core Architecture, RISC V, Power PC, etc.
- Experiences in all aspects of DFT, including scan & ATPG, memory BIST, logic BIST, analog test, and post-silicon support.
- High Speed Peripherals like DDR, PCIe, Ethernet, GPU, VPU (Video Processing Unit).
- NIC/FlexNOC interconnect, Flash memory subsystem architecture knowledge.
- Strong domain knowledge of Clocking, System modes, Power management, Debug, security and other architectures.
- Experience of working on Gate Level Sims with strong concepts of CDC, RDC, Power Aware GLS.
- Low Power intent design and verification using CPF, UPF.
- FPGA/Emulation/Prototyping using HAPS/Palladium/Zebu would be an additional advantage.
- Deep understanding of SOC integration, verification, and Design-for-Test methodologies and tools.
SoC Digital Design Engineer
Location: Shanghai
(上下滑动启阅)
Responsibilities:
- As part of SoC digital design and integration team, work with Architect team closely to build the subsystem for ARM-based SoC.
- Be responsible for the entire digital flow of the SoC subsystem design, including Key IP landing, subsystem integration, design rule check, timing and power analyst.
- Be RTL designer for some digital IPs.
- May also take some verification tasks for SOC subsystem and digital IPs.
Requirements:
- Master degree or above, major in Electronic Engineering/Computer Science or other related discipline.
- Have 1-5 years of hands-on experience in digital SoC/ASIC/IP development.
- Strong Verilog and C coding skills.
- knowledge of on-chip bus protocols: AMBA, AXI or similar.
- Extensive knowledge and experience in front-end implementation tasks such as constraint definition (timing & power), synthesis, power analysis, equivalence checking and STA is a plus.
- Knowledge of DDR protocol is a plus.
- Good English communication skills.
SoC Digital Design and Integration Engineer
Location: Shanghai
(上下滑动启阅)
Responsibilities:
- Involve in ARM based SoC chip development, verification/debug/customer technical support.
- Complete whole chip integration and SoC IP design, integrate digital/analog and third-party IP, design SoC IP(clock/reset/low power/ioring/pacakge), go through SoC flow(UPF/LEC/CLP/LINT/ECO).
- Participate in logic synthesis and timing analysis.
- Write technical documents as required.
Requirements:
- Master degree or above, major in Electronic Engineering/Computer Science or other related discipline.
- Skills in tcl/shell/perl/python script.
- Familiar with Verilog/VHDL/SV, able to RTL design and verification.
- Understand STA timing analysis and SDC constraint.
- Nice to grasp low power design(CPF/UFP) and CLP flow.
- Knowledge in AMBA AXI/AHB/ACE protocol, deep learning in ARM instruction/MMU/interrupt is plus.
- Excellent verbal and written communication skills.
Digital Design Engineer
Location: Shanghai
(上下滑动启阅)
Responsibilities:
- Work with system architecture to define the function and algorithm of mixed signal IP.
- Logic design, implementation & verification by Verilog for mixed signal IPs.
- Testbench generation, verification test pattern development and simulation on module/chip.
- Participate in logic synthesis, DFT, timing analysis and closure.
- Independently solve technical issues and find the solutions.
- Write the technical documents/papers as required.
- Cooperate with and provide support to other functional teams (S&A,SW,TE/PE) in the NPI execution.
Requirements:
- Master degree or above, major in Electronic Engineering/Computer Science or other related discipline.
- Solid background with ASIC design verification flow and multiple ASIC tape out experience.
- Complex IP/ASIC/SoC design verification background, mixed signal design/verification is plus.
- Familiar with System Verilog/UVM for testbench creation, debug, reuse, constrained-random stimulus and functional coverage.
- Solid knowledge on System Verilog, C/C++, Verilog.
- Good communication skills and team work.
- Good oral and written English skills.
SoC Design Engineer
Location: Suzhou
(上下滑动启阅)
Responsibilities
- Main responsibility on SoC design for MCU, MPU with security and connectivity, which targets IoT/Edge/Auto application.
- Responsibility on quality of SoC design with quality check flow, such as LINT/CDC/RDC/CLP.
- Work closely with other function teams on architecture definition as well as power/timing analysis.
- Join our design methodology innovation for application.
Requirements
- Master degree or above, major in Electronic Engineering/Computer Science or other related discipline.
- Understand digital design and verification flow.
- Excellent problem analyzing/solving skills. Good collaboration skillset to support global projects.
- Hard working and team player.
- Good knowledge in C language, Verilog/VHDL/System Verilog.
- Nice to have knowledge of script language (ex. Perl/TCL/Python).
- Nice to have know-how of ARM or AMBA system.
Design Emulation and Validation Engineer
Location: Suzhou
(上下滑动启阅)
Responsibilities:
- Define the Emulation(FPGA/Zebu/Veloce) development plan according to the requirement from the different functional team.
- Build and delivery Emulation(FPGA/Zebu/Veloce) platform to other functional team before silicon coming back
- Create and execute Pre-Si and Post-Si validation plan based on the technical specification
- Co-work with global functional team to investigate and identify the digital or analog design issues.
Requirements:
- Bachelor degree or above, major in Electronic Engineering/Computer Science or other related discipline.
- Familiar with Xilinx device structure & synplicity tools (synplify_premier, identify, certify) & Xilinx PAR tools.
- Experienced in FPGA design & simulation environment setup.
- Good understanding of the FPGA timing, FPGA clocking.
- Must be proficient in Verilog HDL.
- Familiar with logic simulators and debug tools (VCS, NCSIM, Verdi and etc.).
- Working knowledge in C/C++, Makefile.
- Experience in ARM M0+, M4 and M7 based MCU is a strong plus.
- Experience in Keil, IAR or CodeWarrior debugger tool is a strong plus.
- Fluent English (both written and spoken) and excellent communication skills.
- Ability to write professional and technical reports and procedures.
Analog/Mixed Signal Design Engineer
Location: Suzhou
(上下滑动启阅)
Responsibilities
- Responsible for analog / mixed-signal IP design for ARM-based MCU/MPU product development
- Independent IP schematic design / analog & mix-signal simulation/ layout design / IP view generation / technical documentation
- Work with SoC / Backend team on IP integration.
- Work with test/validation/qualification team on IP validation, characterizations and failure analysis.
Requirements
- Bachelor degree or above, major in Electronic Engineering/Computer Science or other related discipline.
- 1-3 years’ relevant analog / mixed-signal IP design experience.
- Familiar with analog/mixed-signal IP design, simulation, integration and validation flow with industrial standard EDA tools and test equipment.
- Familiar with design EDA tool: Cadence Virtuoso, Hspice/Spectre, Calibre, Matlab, QRC , etc.
- Experience in high performance PMU / Data-Conversion / Clocking / OPAMP design is a plus.
- Good communication skills and teamwork for global projects support.
SoC/IP Frontend Design & Verification Engineer
Location: Suzhou
(上下滑动启阅)
Responsibilities:
- Develop RTL for Digital IPs or Subsystems for Industry-IoT/Consumer/Automotive Processor SoC based on Architectural Requirements.
- Build testbench, create tests to verify digital IPs, and then report coverage of verification.
- Develop functional timing constraints for IPs.
- Run IP check flows of Lint, CDC, Synthesis, etc.
Requirements:
- Master’s degree in Microelectronics, Electronics, Electrical Engineering, Computer Science or relevant disciplines
- Minimum 4 years of work experience in RTL Design and Verification.
- Mandatory Tool Exposure: NCSim/VCS, Spyglass or Questa LINT/CDC
- Mandatory Skills: Verilog/System Verilog
- Automation Tools: Shell, TCL, Perl, Python, etc.
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