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恩智浦是嵌入式控制器领域的领先供应商，在工业和消费电子市场都拥有深厚的根基。我们在8位、16位和32位平台上拥有广泛的MCU产品组合，具有领先的低功耗、模拟、控制和通信IP功能。产品组合可支持网络、汽车、消费电子和工业等诸多领域的应用。
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Analog
01
Analog Design Engineer
Location: Shanghai
(滑动浏览岗位详情)
Responsibilities:
- Carry out development activities for analog IP.
- Evaluate the silicon with test team to meet specification.
- Guarantee the technical deliverables of his/her jobs in terms of quality and time.
- Work with design lead and other teammates to meet project goal.
- Develop his/her competence on his/her domain of skills and actions.
Requirements:
- Master degree or above, major in microelectronics, electronic engineering, computer science or relevant disciplines.
- Have 0-2 years' related working experience.
- Solid knowledge of analog circuit design.
- Familiar with the Cadence design tools, such as Virtuoso, Spectre, AMS, etc.
- Prefer know-how of power system, such as switching converter, battery charger, etc.
- Good communicator in both oral and written English.
- Team player, able to work in a cross-functional-team environment.
- Initiative and responsible.
02
Analog Design Engineer
Location: Tianjin
(滑动浏览岗位详情)
Responsibilities:
- Be responsible to design analog mixed signal power ICs for automotive and power management applications. This includes system definition, IC architecture, circuit design, simulation and layout. All aspects require good engineering skills together with analysis, creativity, collaboration and customer interaction.
- Write articles for technical publications and conferences, and provide email and phone support for assigned products.
- Documentation for design reviews and design notes, layout guidance, and other cell design activities.
Qualifications:
- Bachelor degree or above, major in electrical engineering or other related disciplines.
- Minimum 5 years’ direct experience designing analog and mixed-signal transistor level circuitry for power management applications.
- Must have expertise in analog circuit design theory and device physics and have used this to create original and novel circuits that provide significant value.
- Ability to design traditional analog MOS and BJT circuits such as bandgap references, amplifiers, oscillators, detection circuits, linear LDO and switching regulators.
- Ability to design DC-DC charger, fuel gage, coulomb counter or ADC will be a great additional skills required for the position.
- Other desirable skills include understanding ESD and EMC (Electromagnetic Compatibility) techniques and testing procedures, experience with mixed-signal design tools and flow, reading and writing Verilog AMS models.
03
Analog Layout Engineer
Location: Tianjin
(滑动浏览岗位详情)
Responsibilities:
- Designing complex layout for mixed signal, and analog circuits in deep sub-micron CMOS technologies.
- Reviewing and analyzing floorplans and complex circuits with circuit designers.
- Working with circuit design team to plan/schedule work and negotiate any necessary layout tradeoffs as needed.
- Reviewing LVS, DRC and ERC reports to solve any issue.
- Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirements.
- Collaborating with SoC backend team to guarantee Analog IP release quality.
Requirements:
- Bachelor degree or above, major in electrical engineering or other related disciplines.
- Minimum 3 years’ analog layout experience.
- Understanding of analog and mixed signal design and layout.
- Experience implementing analog layouts to achieve tight matching, low noise, and low power consumption.
- High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. reports.
- Knowledge of CADENCE layout tools
- Scripting skills in PERL or SKILL are considered a plus, but not required.
- Excellent communication skills and able to work with cross-functional teams.
Design & Verification
01
MSIP Digital Design Engineer
Location: Suzhou
(滑动浏览岗位详情)
Responsibilities:
- Work with analog designer and system architecture to define the digital part for MSIP/ sub-system, including the functionality and algorithm.
- Implement RTL design with high quality in gate count reduction, DFT coverage and timing closure.
- Implement digital part verification and IP level mixed signal verification.
- Work with analog designer on MSIP view generation and documentation delivery.
- Support SoC level integration / verification / silicon validation.
Requirements:
- Master degree or above, major in electrical engineering or other related disciplines.
- 3-5 years‘ digital design and verification experience.
- Good knowledge in Verilog, VHDL, System Verilog, System C or E, and script language.
- Familiar with Unix/Linux system and EDA tool from Cadence, Synopsis, Mentor for digital and analog development.
- Experience with one or more of the following is a plus: power management, 8bit, 16bit or 32bit Micro-controller, ARM or AHB bus system, script languages.
- Basic knowledge of analog and mix-signal design and simulation is a plus.
- Good communication skills and teamwork for global projects support.
02
SoC Design & Verification Engineer
Location: Suzhou
(滑动浏览岗位详情)
Responsibilities
- Main responsibility on SoC design for MCU/MPU with security and connectivity, which targets IoT/Edge/Auto application.
- Responsibility to design subsystem and top logic/integration for SoC.
- Responsibility on quality of SoC design with quality check flow, such as LINT/CDC/RDC/CLP.
- Support IP design and SoC verification.
- Work closely with other function teams on architecture definition as well as power/timing analysis.
- Join design methodology innovation for application
Requirements
- Bachelor degree or above, majoring in Microelectronics, electronic engineering, computer science or relevant disciplines.
- Minimum 3 years' related working experience.
- Experience on design or verification with Verilog/SV/VHDL.
- Understand SoC digital design and verification flow.
- Excellent problem analyzing/solving skills. Good collaboration skillset to support global projects. Hard working and team player.
- Good knowledge in C language, Verilog/VHDL/System Verilog.
- Nice to have knowledge of script language (ex. Perl/TCL/Python).
- Nice to have know-how of ARM or AMBA system.
03
SoC Design & Verification Engineer
Location: Shanghai
(滑动浏览岗位详情)
Responsibilities:
- Work with the global design teams to do complex SoC verification for digital/analog design.
block level verification based on System Verilog & UVM methodology for the complex new IP design and SoC fabric verification.
- Responsible for verification plan quality, verification result/design target cross-check, test case development to have better coverage and verification quality. Co-work with functional verification team to ensure the complex SoC verification functional coverage and quality.
Requirements
- Bachelor degree or above, majoring in Microelectronics, electronic engineering, computer science or relevant disciplines.
- Minimum 10 years' related working experience.
- Good knowledge and experience in C/C++/Verilog/System Verilog/UVM programming languages, familiar with IC simulation & debug flow and tools, testbench build, unix/linux environment, tcl/perl script etc.
- Solid UVM experiences are required.
- Good Knowledge of computer architecture, especially ARM CPU(Cortex A/M series), bus protocols(APB/AHB/AXI), verification experience of ARM-based SoC is a plus.
04
Senior Digital Verification Engineer
Location: Shanghai
(滑动浏览岗位详情)
Responsibilities:
- Be responsible for the complete functional verification at block level and chip level.
- Interface to HW and SW design teams, as well as to architecture and system teams, to understand functionality and application of the IP / system.
- Develop, debug, and modify the test environment for different platforms (RTL, Gate, FPGA).
- Define the verification strategy and plan.
- Define and code test cases in an appropriate language and debug these test cases.
- Define goals for the verification coverage, implement appropriate methods to measure the verification coverage, and enhance the test cases until coverage goals are met.
- Interface and support to validation and product engineering teams for silicon correlation and debug.
Requirements：
- Bachelor degree or above, majoring in Microelectronics, electronic engineering, computer science or relevant disciplines.
- Minimum 5 years' related working experience.
- Experience of designing and implementing verification environments for complex RTL designs.
- Good knowledge and experience in hardware verification, well-versed in use of hardware verification languages e.g system Verilog and verification methodology such as UVM.
- Understanding of end-to-end verification processes, from test plan creation through to verification closure.
- Good analytical and debugging skills.
- Good Communication skills (Written and Verbal). Fluent English and native Mandarin are required.
Validation
01
Design Emulation & Validation Engineer
Location: Suzhou
(滑动浏览岗位详情)
Responsibilities:
- Define the Emulation(FPGA/Zebu/Veloce) development plan according to the requirement from the different functional team.
- Build and delivery Emulation(FPGA/Zebu/Veloce) platform to other functional team before silicon coming back.
- Create and execute Pre-Si and Post-Si validation plan based on the technical specification.
- Co-work with global functional team to investigate and identify the digital or analog design issues.
Requirements:
- Bachelor degree or above, major in electrical/computer engineering or relevant disciplines.
- Have 0-2 years' related working experience.
- Familiar with Xilinx device structure & synplicity tools (synplify_premier, identify, certify) & Xilinx PAR tools.
- Experienced in FPGA design & simulation environment setup.
- Good understanding of the FPGA timing, FPGA clocking.
- Must be proficient in Verilog HDL.
- Familiar with logic simulators and debug tools (VCS, NCSIM, Verdi and etc.).
- Working knowledge in C/C++, Makefile.
- Experience in ARM M0+, M4 and M7 based MCU is a strong plus.
- Experience in Keil, IAR or CodeWarrior debugger tool is a strong plus.
- Fluent English (both written and spoken) and excellent communication skills.
- Ability to write professional and technical reports and procedures.
02
Jr. SoC Design Validation Engineer
Location: Tianjin
(滑动浏览岗位详情)
Responsibilities:
- Be responsible for validating each block of SoC functionality based on MCU/MPU(Coretx-M/A) reference manual and reporting the bugs in chip or system level.
- Perform post-silicon validation activities including preparation of validation plans and coding of test cases and validation execution, MCU/MPU(Coretx-M/A) reference manual review, and validation report release.
- Reproduce design tickets/issues and assist design team in debugging and root cause analysis.
- Run multiple projects with aggressive schedules in a fast paced environment.
Requirements:
- Bachelor degree or above, majoring in Microelectronics, electronic engineering, computer science or relevant disciplines.
- Have 0-2 years' related working experience.
- Deep understanding of ARM based MCU/MPU(Coretx-M/A) architecture and system application
- Familiar with embedded popular IDE tools, e.g. ADS/DS-5, IAR, Keil, CodeWarrior.
- Hands on experience with Lab equipment such as oscilloscope, logic analyzers and multi-meter.
- Good at developing and debugging of the ARM based embedded system.
- Good at C coding and compiler, knowledge on IC design is a plus.
- Experience in automation environments such as LabView is a plus.
- Fluent in English reading and writing, good at English communication skills.
- Experience of USB2.0/3.0 and Ethernet protocol is a plus.
Verilog/System Verilog HDL knowledge is a plus.
- Python or C++ programming skill is a plus.
- Good English reading, writing and communication skills.
- Excellent communication skill and team work oriented.
03
Sr. SoC Design Validation Engineer
Location: Tianjin
(滑动浏览岗位详情)
Responsibilities:
- Be responsible for developing validation plan, testcase, and validation the functionality to meet design spec. Also work on FPGA/Zebu implementation for chip prototyping to enable SW development during pre-silicon activity.
- Perform post-silicon validation activities including preparation of validation plans and coding of test cases and validation execution, MCU/MPU(Coretx-M/A) reference manual review, and validation report release.
- Perform pre-silicon validation activities in emulation environment to pre-coding validation test case and design issue debug.
- Co-work with design and internal team for issue debugging and root cause analysis.
- Customer issues support with internal team.
Requirements:
- Bachelor degree or above, majoring in Microelectronics, electronic engineering, computer science or relevant disciplines.
- Minimum 4 years’ related working experience
- Understanding of ARM based MCU/MPU(Coretx-M/A) architecture and system application.
- Familiar with embedded popular IDE tools, e.g. ADS/DS-5, IAR, Keil, CodeWarrior
- Good at developing and debugging of the ARM based embedded system.
- Good experiences on high speed interface functional or compliance test, like DDR, PCIe, USB, MIPI, LVDS and etc is a plus.
- Good at C coding and compiler, knowledge on IC design is a plus.
- Experience in automation environments such as LabView is a plus.
- Verilog/SystemVerilog HDL knowledge is a plus.
- Python or C++ programming skill is a plus.
- Good English reading, writing and communication skills.
- Excellent communication skill and team work oriented.
Backend
01
SoC Backend Design Engineer
Location: Tianjin
(滑动浏览岗位详情)
Responsibilities:
- Work closely with SoC team (architects, logic designers, etc) for chip/block level physical designs.
- Responsible for chip and block level low power definition, RTL synthesis, logic/power equivalent check, clock tree synthesis, P&R, STA/timing noise closure, etc.
- Responsible for die size estimation, floor-plan and power/IR analysis, DRC/LVS, etc.
Requirements:
- Bachelor or master degree, majoring in microelectronics, electronic engineering , computer science or relevant disciplines.
- Minimum 2 years' related working experience.
- Good knowledge and experience in SoC backend design and EDA tools.
- Script coding ability of C/C++, Perl/TCL, in Linux/Unix environment.
- Excellent communication skills and collaboration spirit.
- Basic knowledge of SoC frontend and DFT is preferred.
02
Sr. SoC Backend Design Engineer
Location: Suzhou
(滑动浏览岗位详情)
Responsibilities:
- Work closely with SoC team (architects, logic designers, etc) for chip/block level physical designs.
- Responsible for chip and block level low power definition, RTL synthesis, logic/power equivalent check, clock tree synthesis, P&R, STA/timing noise closure, etc.
- Responsible for die size estimation, floor-plan and power/IR analysis, DRC/LVS, etc.
Requirements:
- Bachelor or master degree, majoring in microelectronics, electronic engineering , computer science or relevant disciplines.
- Minimum 3 years’ experience in SoC backend design and EDA tools.
- Script coding ability of C/C++, Perl/TCL, in Linux/Unix environment.
- Excellent communication skills and collaboration spirit.
- Knowledge of SoC frontend and DFT is preferred.
DFT
01
SoC DFT Engineer
Location: Suzhou
(滑动浏览岗位详情)
Responsibilities:
- Setup and maintain DFT flow, familiar with script language.
- Be responsible for definition and implementation different schemes of DFT aspects: including scan/MBIST/JTAG insertion, ATPG generation, test patterns generation.
Requirements:
- Bachelor or master degree, majoring in microelectronics, electronic engineering , computer science or relevant disciplines.
- Minimum 3 years’ related working experience.
- Proficiency in whole DFT architecture definition.
- Experience RTL/netlist simulation, good debug capability , familiar with Verilog.
- Experience with ATE on-line debugging and DFT diagnosis.
- Experience with Post-silicon DPPM improvement , coverage hole analysis.
02
SoC DFT Engineer
Location: Tianjin
(滑动浏览岗位详情)
Responsibilities:
- Participate in definition of both chip level and block level design-for-test structure and methodology.
- Responsible for ATPG and model creation, memory Built in Self-Test, Embedded Deterministic Test and Boundary Scan Test.
- Work closely with design engineer for design optimization for test coverage improvement, test volume and test time reduction.
- Responsible for scan/bist pattern simulation based on timing files and gate-level netlist.
- Work closely with Test Engineer to debug and solve scan/bist pattern failures on tester.
- Work as a global team to do complex SoC design and test.
Requirements:
- Bachelor or master degree, majoring in microelectronics, electronic engineering , computer science or relevant disciplines.
- Minimum 3 years’ related working experience.
- Excellent communication skills and collaboration spirit.
MCU SoC Architect
Location:Suzhou
(滑动浏览岗位详情)
Responsibilities:
- Define and specify the SoC architecture for advanced microcontrollers (MCUs) to meet the product requirements.
- Work with SoC team to understand and define implementation decisions, perform implementation reviews, and understand trade-offs between power consumption, performance, cost, and schedule.
- Define, specify, and architect analog IP blocks (plus digital wrappers) and work with analog IP team in making implementation trade-offs.
- Define, specify, and architect digital IP blocks and work with digital IP team in making implementation trade-offs.
- Technical interface for Marketing, Systems and Applications teams.
- Interface with DFT, Security, Functional Safety and Software teams to ensure SoC architecture meets all product related requirements.
Requirements:
- Master’s degree in Electronics/Electrical Engineering or Computer Science (or equivalent).
- Minimum 12 years’ experience in SoC architecture, RTL design, SoC integration or related fields.
- Familiar with MCU SoC Architecture.
- Good team player, can collaborate with others in cross-functional teams.
- Good problem-solving skills and communication skills.
Preferred:
- Experience with Verilog, SystemVerilog or VHDL is an advantage.
- Familiar with ARM Cortex-M cores; knowledge of TZ-M is an advantage.
- Experience with advanced low power techniques.
- Experience with Synthesis, Static Timing Analysis and related tools is an advantage.
- Experience with integrating NVM, analog convertors and power management controllers.
- Knowledge of security concepts with high-level understanding of cryptographic algorithms is an advantage.
- Knowledge of industrial safety concepts and standards is an advantage.
- Software programming experience on microcontroller-class devices is an advantage.
Technical Program Manager
Location:Tianjin / Suzhou
(滑动浏览岗位详情)
Responsibilities:
- Play a key role in driving various activities surrounding the SoC development in alignment high quality deliverable requirements.
- Lead all phases of various SoC projects from architectural definition to validation.
- Create project plans with milestones, timelines, and ownership, and drive delivery.
- Facilitate related project calls with global cross-functional teams, drive progress and resolve issues.
- Facilitate project health check awareness and support executive/senior management reporting.
- Work with internal and external partners to drive connectivity software and hardware integration and collaboration activities.
- Act as the first line of contact for issue escalation.
- Provide balance in technical support for architectural approvals, development, documentation closure and source control management (quality control).
- Ensure that the team is effectively delivering on their objectives and all the plans are on track. Perform risk analysis, identify and execute on mitigation steps.
Requirements:
- Bachelor or master degree, majoring in microelectronics, electronic engineering , computer science or relevant disciplines.
- Minimum 7 years’ experience in embedded hardware design methodologies.
- Deep knowledge in project management.
- Business fluency in English is a prerequisite.
- Experienced Manager with proactive and solution-oriented approach.
- Ability to drive business and innovation.
- Strong analytical skills and familiarity with complex environments.
- Good training and presentation skills.
- Good communication and leadership skills.
- Experience with Project Management tools such as MS Project or similar.
- General understanding in system design and architectural definition.
- Experience in working with engineering experts in a multi geography, multi-cultural environment.
- Proven strong leadership skills, team player, able to challenge the status quo and capable to switch between detail and helicopter view.
- Flexible, calm under pressure, and comfortable taking ownership in ambiguous environments.
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