社招 | 大批芯片设计热招岗位袭来！
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上周我们推出了“恩”多热招职位，不知道大家有没有找到合心意的岗位呢？今天小编给你们带来了更多芯片设计相关岗位。快来看看有没有你心仪的吧！恩智浦期待你的加入！
如何申请？
申请方式①
将简历投递至：talent@nxp.com
邮件注明：姓名+申请职位+工作城市
申请方式②
点击文末"阅读全文"，
找到职位，输入职位编号(R-100*****)
进行申请！
Principal SoC Digital Front-End Design Engineer
Location: Shanghai
R-10029858
点击展开职位描述
Responsibilities:
• SoC top level or subsystem architecture definition, IP Integration and RTL logic coding.
• Subsystem clock structure definition, timing constrain generation.
• Implement low power design for SoC subsystems.
• Perform related design check include Lint/CDC/CLP.
• Develop SoC verification patterns.
• Support Backend design team for SoC signoffs.
Qualifications:
• Master’s degree, major in relevant disciplines.
• Over 2 years of hands-on experience in digital SoC/ASIC/IP development.
• Strong Verilog and C coding skills
• Familiar with on-chip bus protocols: AXI/AHB or similar.
• Experience in front-end implementation such as constraint definition (timing & power), synthesis, power analysis, equivalence checking and STA is a plus.
• Good English communication skills.
Senior Principal MCU SoC Architect
Location: Shanghai/Suzhou
R-10028025
点击展开职位描述
Responsibilities:
• Define and specify the SoC architecture for advanced microcontrollers (MCUs) to meet the product requirements.
• Work with SoC team to understand and define implementation decisions, perform implementation reviews, and understand trade-offs between power consumption, performance, cost, and schedule.
• Define, specify, and architect analog IP blocks (plus digital wrappers) and work with analog IP team in making implementation trade-offs.
• Define, specify, and architect digital IP blocks and work with digital IP team in making implementation trade-offs.
• Technical interface for Marketing, Systems and Applications teams.
• Interface with DFT, Security, Functional Safety and Software teams to ensure SoC architecture meets all product related requirements.
Qualifications:
• Master’s degree in Electronics/Electrical Engineering or Computer Science (or equivalent).
• 12+ years’ experience in SoC architecture, RTL design, SoC integration or related fields.
• Familiar with MCU SoC Architecture.
• Good team player, can collaborate with others in cross-functional teams.
• Good problem-solving skills and communication skills.
Preferred Qualifications:
• Experience with Verilog, SystemVerilog or VHDL is an advantage.
• Familiar with ARM Cortex-M cores; knowledge of TZ-M is an advantage.
• Experience with advanced low power techniques.
• Experience with Synthesis, Static Timing Analysis and related tools is an advantage.
• Experience with integrating NVM, analog convertors and power management controllers.
• Knowledge of security concepts with high-level understanding of cryptographic algorithms is an advantage.
• Knowledge of industrial safety concepts and standards is an advantage.
• Software programming experience on microcontroller-class devices is an advantage.
Principal Analog/ Mixed-Signal IP Design Engineer
Location: Suzhou
R-10029667
点击展开职位描述
Responsibilities:
• Work within Solutions & Connectivity Innovation segment of Edge Processing BL to develop and integrate new embedded AI/ML based voice and vision IoT solutions.
• Work closely and partial time need onsite support local customers for their product development and trouble shooting from concept stage to mass production.
• Work as software application engineer to support product marketing, FAE and distributor teams to resolve turnkey IoT solutions technical issues.
• Support designers, system architecture engineers and product marketers for new product definition and architectural proposals.
• Translate customer / market requirements into technical languages.
• Investigate and analyze consumer and industrial market applications and competitors’ solutions.
• Document, design, and prototype system level technical application requirements.
Qualifications:
• Master's degree, major in Microelectronics, Electronics, Electrical Engineering, Computer Science or relevant disciplines with at least 6 years related working experience.
• Solid skills for C/C++ & Python programming and real coding capability with GIT SCM experiences, Better to have github contribution knowhow.
• Rich experience for working with embedded Linux or FreeRTOS / Zephyr etc. OS which widely used for MPU and MCU platform.
• Experience with and willingness to gain deep technical knowledge around connectivity, edge compute and machine learning for software and systems design.
• Excellent communications and presentation skills and good command of English for listening, speaking, reading and writing. Prefer with multi-nation company working experience.
• Prefer to have real experience for object / facial recognition, voice recognition AI/ML based product design and development.
• Prefer to have knowledge of one or more wireless connectivity like WiFi/BLE/NFC/UWB etc. for software application design.
• Flexible thinker with track record of innovation, Entrepreneurial spirit – fast moving and sense of urgency.
Principal SoC Design Engineer
Location: Suzhou
R-10029856
点击展开职位描述
Responsibilities:
• Main responsibility on SoC design for MCU/MPU with security and connectivity, which targets IoT/Edge/Auto application.
• Responsibility to design subsystem and top logic/integration for SoC.
• Responsibility on quality of SoC design with quality check flow, such as LINT/CDC/RDC/CLP.
• Support IP design and SoC verification.
• Work closely with other function teams on architecture definition as well as power/timing analysis.
• Join design methodology innovation for application.
Qualifications:
• Master's degree, majorin Microelectronics, electronic engineering, computer science or relevant disciplines.
• Experience on design or verification with Verilog/SV/VHDL.
• Understand SoC digital design and verification flow.
• Excellent problem analyzing/solving skills. Good collaboration skillset to support global projects. Hard working and team player.
• Good knowledge in C language, Verilog/VHDL/System Verilog.
• Nice to have knowledge of script language (ex. Perl/TCL/Python).
• Nice to have know-how of ARM or AMBA system.
Principal SoC Verification Engineer Engineer
Location: Suzhou
R-10033585
点击展开职位描述
Responsibilities:
• Responsible on frontend SoC verification work for ARM based MCU and MPU products..
• Work on SoC level verifications, run RTL&UPF simulations for low power related verifications.
• Work closely with backend and other function teams on architecture definition as well as power/timing analysis.
• Join our design and verification methodology innovation which include testbench development, formal verification, security verification, mixed signal verification, core& platform verification.
• Work closely with validation , test engineer on post silicon issue debug.
Qualifications:
• Master’s degree, major in Microelectronics, Electronic engineering , Computer science or relevant disciplines.
• Have knowledge about EDA simulation and VLSI design flow.
• Good knowledge in C language, Verilog/VHDL/System Verilog.
• Have knowledge about computer architecture, 8bit, 16bit or 32bit Micro-controller or Micro-processer.
• Nice to have knowledge of script language (ex. Perl/Python).
• Nice to have know-how of ARM or AHB bus system.
Senior Design Emulation and Validation Engineer
Location: Suzhou
R-10029877
点击展开职位描述
Responsibilities:
• Define the Emulation(FPGA/Zebu/Veloce) development plan according to the requirement from the different functional team.
• Build and delivery Emulation(FPGA/Zebu/Veloce) platform to other functional team before silicon coming back.
• Create and execute Pre-Si and Post-Si validation plan based on the technical specification.
• Co-work with global functional team to investigate and identify the digital or analog design issues.
Qualifications:
• Bachelor or master degree in electrical/computer engineering or relevant disciplines.
• Familiar with Xilinx FPGA device structure & synplicity tools (synplify_premier, identify, certify) & Xilinx PAR tools.
• Experienced in FPGA design & simulation environment setup.
• Good understanding of the FPGA timing, FPGA clocking.
• Must be proficient in Verilog HDL.
• Familiar with logic simulators and debug tools (VCS, NCSIM, Verdi and etc.).
• Working knowledge in C/C++, Makefile.
• Experience in ARM M0+, M4 and M7 based MCU is a strong plus.
• Experience in Keil, IAR or CodeWarrior debugger tool is a strong plus.
• Fluent English (both written and spoken) and excellent communication skills.
• Ability to write professional and technical reports and procedures.
Senior Digital IP Design Engineer
Location: Suzhou
R-10028566
点击展开职位描述
Responsibilities:
• Develop RTL for digital IPs or subsystems based on architectural requirements.
• Build testbench, create tests to verify digital IPs, and then report coverage of verification.
• Develop functional timing constraints for IPs.
• Run IP check flows of Lint, CDC/RDC, DFT, Synthesis, etc.
Qualifications:
• Master's degree, major in Microelectronics, Electronics, Electrical Engineering, Computer Science or relevant disciplines.
• Over 5 years of experience in RTL Design and Verification.
• Mandatory Tool Exposure: NCSim/VCS, Spyglass or Questa LINT/CDC.
• Mandatory Skills: Verilog/SystemVerilog.
• Automation Tools: Shell, TCL, Perl, Python, etc.
SoC Design Engineer
Location: Suzhou
R-10029844
点击展开职位描述
Responsibilities:
• Main responsibility on SoC design for MCU/MPU with security and connectivity, which targets IoT/Edge/Auto application.
• Responsibility to design subsystem and top logic/integration for SoC.
• Responsibility on quality of SoC design with quality check flow, such as LINT/CDC/RDC/CLP.
• Support IP design and SoC verification.
• Work closely with other function teams on architecture definition as well as power/timing analysis.
• Join design methodology innovation for application.
Qualifications:
• Master's degree, major in Microelectronics, electronic engineering, computer science or relevant disciplines.
• Experience on design or verification with Verilog/SV/VHDL.
• Understand SoC digital design and verification flow.
• Excellent problem analyzing/solving skills. Good collaboration skillset to support global projects. Hard working and team player.
• Good knowledge in C language, Verilog/VHDL/System Verilog.
• Nice to have knowledge of script language (ex. Perl/TCL/Python).
• Nice to have know-how of ARM or AMBA system.
Design Quality - Verification Engineer
Location: Tianjin
R-10032283
点击展开职位描述
Responsibilities:
• The Verification Engineer is part of the Design Quality team responsible for design support of products currently in production. Focus is on the analysis and debug of customer issues to determine root cause of functional verification test coverage gaps. Responsibilities encompass the enhancement of functional verification test benches, debugging failures, and assessing and implementing new functional test patterns to improve quality test coverage in existing production devices. A “zero-defect” mindset is a key enabler.
Qualifications:
• Master's degree in relevant disciplines.
• Over 5 years of experience in functional verification.
• Test pattern debugging and testing for verification and automatic testers.
• C/C++/Assembly Language Programming skills in ARM A/R/M series.
• VHDL/Verilog/System Verilog.
• OVM/UVM, Class based verification methodologies.
• Scripting - PERL, Python, UNIX/LINUX.
• Experience working closely with post-silicon teams (test engineering and failure analysis) is a plus.
• Excellent written and verbal communication skills in English.
Design Quality - Verification Engineer Lead
Location: Tianjin
R-10032285
点击展开职位描述
Responsibilities:
• The Verification Engineer is part of the Design Quality team responsible for design support of products currently in production. Focus is on the analysis and debug of customer issues to determine root cause of functional verification test coverage gaps. Responsibilities encompass the enhancement of functional verification test benches, debugging failures, and assessing and implementing new functional test patterns to improve quality test coverage in existing production devices. A “zero-defect” mindset is a key enabler.
Qualifications:
• Master’s degree in relevant disciplines.
• Over 10 years of experience in functional verification.
• Test pattern debugging and testing for verification and automatic testers.
• C/C++/Assembly Language Programming skills in ARM A/R/M series.
• VHDL/Verilog/System Verilog.
• OVM/UVM, Class based verification methodologies.
• Scripting - PERL, Python, UNIX/LINUX.
• Experience working closely with post-silicon teams (test engineering and failure analysis) is a plus.
• Excellent written and verbal communication skills in English.
Security Hardware Design Engineer
Location: Tianjin
R-10032794
点击展开职位描述
Responsibilities:
• Design and verification of cryptographic & security hardware IPs.
• Developing IPs for OSCCA standards, especially SM2, SM3 and SM4.
• Implementation of security countermeasures to protect IP against side channel and fault attacks.
• Drive innovation on way of working in secure HW design, especially secure design flow and methodology.
Qualifications:
• Bachelor's degree or above, major in Electrical Engineering.
• Over 8 years of experience of developing cryptographic IPs.
• Knowledge of security threats such as side channel or fault attacks and potential mitigations.
• High level of experience in ASIC design.
• Experience with RTL development in Verilog, synthesis, static timing analysis.
• IP verification and knowledge of UVM an advantage.
• Very good English communication skills and a pro-active attitude.
Security Hardware IP Team Lead
Location: Tianjin
R-10032614
点击展开职位描述
Responsibilities:
• Managing a small team of dedicated security experts in the development of security and cryptographic IPs.
• Design of hardware architectures with respect to cryptographic & security aspects.
• Set goals and provide mentorship and technical guidance for your team.
• Have special responsibility for architecting, implementing and verifying OSCCA cryptographic IPs such as SM2, SM3 and SM4.
• Drive innovation on way of working in secure HW design, especially secure design flow and methodology.
Qualifications:
• Bachelor's degree or above, major in Electrical Engineering.
• Over 10 years of experience of developing cryptographic IPs.
• Knowledge of security threats such as side channel or fault attacks and potential mitigations.
• High level of experience in ASIC design.
• Experience with RTL development in Verilog, synthesis, static timing analysis.
• IP verification and knowledge of UVM an advantage.
• Very good English communication skills and a pro-active attitude.
Senior SoC implementation Engineer
Location: Tianjin
R-10033989
点击展开职位描述
Responsibilities:
• High performance Micro Processor Synthesis and Static Timing Analysis.
• Padring design, Floorplan, Place&Route and physical verification.
• Power integrity analysis.
• Drive innovative ideas within function and collaborate with local and world-wide functional teams.
Qualifications:
• Bachelor's degree or above, major in Micro Electronics or equivalent.
• Over 5 years of SoC implementation experience in production tape-outs.
• Deep knowledge in semiconductor process technology, digital circuit and SoC implementation methodology.
• Good listen, write and spoken English.
• Enthusiastic, creative, motivated and collaborative.
SoC DFT Engineer
Location: Tianjin
R-10029849
点击展开职位描述
Responsibilities:
• Develop RTL for digital IPs or subsystems based on architectural requirements.
• Build testbench, create tests to verify digital IPs, and then report coverage of verification.
• Develop functional timing constraints for IPs.
• Run IP check flows of Lint, CDC/RDC, DFT, Synthesis, etc.
Qualifications:
• Bachelor's degree or above in Microelectronics, Electronics, Electrical Engineering, Computer Science or relevant disciplines.
• Over 2 years of experience in relevant fields.
• Good knowledge and experience in DFT implementation methodology, flow optimization and DFT coverage improvement. Mentor tool is a plus.
• Strong skills of solving problem, self-motivated and good team player.
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