释放IC设计的创新活力
重新定义智慧未来!
SRAM Design Engineer
(静态随机存储器设计工程师)
工作内容
1. Develop SRAM/ROM compilers and customized macros.
2. Develop SRAM/ROM characterization flow and deliver design kits.
3. Develop Memory compiler tiling code.
职位要求
1. Candidate must have a MS degree or above in Electrical or Computer Engineering
2. Knowledge on transistor level circuit design and layout design
3. Experience in spice simulation or fast spice simulation
4. Familiarity with Verilog and Synopsys .lib
5. Ability in scripting language, such as Perl/Python/shell/tcl
Digital Circuit Design Engineer
(数字电路设计工程师)
工作内容
1. Develop advanced standard cell and GPIO libraries on advanced process technologies (6nm, 7nm, 12/16nm, 22/28nm, etc.).
2. Take challenging tasks from circuit design to SOC design to achieve world-class PPA performance (high-performance, low-power, and area-effective).
职位要求
1. Good knowledge of circuits design. Experience in digital circuit or analog design is preferred.
2. Experience in Cadence/Synopsys/Mentor EDA tools and Linux/Unix environment is preferred.
3. CAD and script capability such as Python/Perl/Shell is preferred.
4. Solid understanding of device scaling challenges and circuit-process technology interactions applicable for advanced FinFET nodes is a plus.
5. Experience in reliability (EM, high-temperature aging effects, etc.) is a plus.
6. Self-motivated and hard work.
Layout Engineer
(IP版图设计工程师)
工作内容
1. Full layout design for standard cell/IO/SRAM IPs in advanced process nodes
2. Work on the physical verification (DRC/LVS/Antenna ...)
3. Work on test chip layout design and verification
4. Close cooperation with designers on PPA optimization
职位要求
1. At least BS Degree of Microelectronics or Physics.
2. Familiar with layout design and verification tools (Virtuoso, Laker, Calibre)
3. Familiar with design rule and layout effect in advanced process.
4. Excellent skills of communication and teamwork are also expected.
5. Programming experience (Perl/tcl skill) will be a plus.
6. Experience in advanced process (n16 and beyond) will be a plus.
DRC/LVS Development Engineer
(DRC/LVS开发工程师)
工作内容
1. Work closely with process RD team to develop DRC/LVS for design readiness.
2. Provide customer support to world-wide leading design house.
3. Initial more innovation to continue optimize development efficiency.
4. Work closely with various departments (Physical design/integration/Device RD/Product/ESD) on their design requirements.
5. Work closely with EDA partner for tool qualification and methodology enhance.
职位要求
1. Good knowledge of semiconductor FEOL/BEOL process and chip design concepts. Solid understanding of device physics, Layout design is a plus.
2. Knowledge of EDA partner (Mentor, Synopsys, Cadence, etc.) tools suite is a plus. Especially Laker /Virtuoso /Calibre.
3. Scripting and programming experience using several of the following: Perl, Python, C, C++, TCL, Skill.
4. Ability to work across teams to drive a solution, problem solver and self-motivated.
5. The ideal candidate will have experience in DRC/LVS development.
6. MS or above in EE, CS related fields.
SPICE Modeling Engineer
工作内容
1. Testkey design for SPICE modeling
2. SPICE model release for advanced and mainstream process
3. Device characterization
4. Customer support
5. Automation development on all SPICE modeling flow
职位要求
1. Minimum MS degree majoring in EE, Physics or Engineering related fields.
2. Related experience in semiconductor device, measurement, extraction and SPICE simulation.
3. Proficiency in programming language, such as Perl or Python or C++ or VB.Net.
4. Must be effectively bilingual in Chinese and English.