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恩智浦是嵌入式控制器领域的领先供应商，在工业和消费电子市场都拥有深厚的根基。我们在8位、16位和32位平台上拥有广泛的MCU产品组合，具有领先的低功耗、模拟、控制和通信IP功能。产品组合可支持网络、汽车、消费电子和工业等诸多领域的应用。
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# Architecture #
01
MCU SoC Architect
Location: Suzhou / Tianjin
(上下滑动启阅)
Responsibilities:
- Define and specify the SoC architecture for advanced microcontrollers (MCUs) to meet the product requirements.
- Work with SoC team to understand and define implementation decisions, perform implementation reviews, and understand trade-offs between power consumption, performance, cost, and schedule.
- Define, specify, and architect analog IP blocks (plus digital wrappers) and work with analog IP team in making implementation trade-offs.
- Define, specify, and architect digital IP blocks and work with digital IP team in making implementation trade-offs.
- Technical interface for Marketing, Systems and Applications teams.
- Interface with DFT, Security, Functional Safety and Software teams to ensure SoC architecture meets all product related requirements.
Requirements:
- Master’s degree in Electronics/Electrical Engineering or Computer Science (or equivalent).
- Minimum 12 years’ experience in SoC architecture, RTL design, SoC integration or related fields.
- Familiar with MCU SoC Architecture.
- Good team player, can collaborate with others in cross-functional teams.
- Good problem-solving skills and communication skills.
Preferred:
- Experience with Verilog, SystemVerilog or VHDL is an advantage.
- Familiar with ARM Cortex-M cores; knowledge of TZ-M is an advantage.
- Experience with advanced low power techniques.
- Experience with Synthesis, Static Timing Analysis and related tools is an advantage.
- Experience with integrating NVM, analog convertors and power management controllers.
- Knowledge of security concepts with high-level understanding of cryptographic algorithms is an advantage.
- Knowledge of industrial safety concepts and standards is an advantage.
- Software programming experience on microcontroller-class devices is an advantage.
# Design #
01
Analog Layout Designer
Location: Tianjin
(上下滑动启阅)
Responsibilities:
- Designing complex layout for mixed signal, and analog circuits in deep sub-micron CMOS technologies.
- Reviewing and analyzing floorplans and complex circuits with circuit designers.
- Working with circuit design team to plan/schedule work and negotiate any necessary layout tradeoffs as needed.
- Reviewing LVS, DRC and ERC reports to solve any issue.
- Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirements.
- Collaborate with SOC Back-end team to guarantee Analog IP release quality.
Requirements:
- Master or bachelor degree, majoring in microelectronics, electronic engineering , computer science or relevant disciplines.
- Over 3 years analog layout experience.
- Understanding of analog and mixed signal design and layout.
- Experience implementing analog layouts to achieve tight matching, low noise, and low power consumption.
- High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. reports.
- Knowledge of CADENCE layout tools.
- Scripting skills in PERL or SKILL are considered a plus, but not required.
- Excellent communication skills and able to work with cross-functional teams.
02
SoC Design Engineer
Location: Suzhou
(上下滑动启阅)
Responsibilities:
- Main responsibility on SoC design for MCU/MPU with security and connectivity, which targets IoT/Edge/Auto application.
- Responsibility to design subsystem and top logic/integration for SoC.
- Responsibility on quality of SoC design with quality check flow, such as LINT/CDC/RDC/CLP.
- Support IP design and SoC verification.
- Work closely with other function teams on architecture definition as well as power/timing analysis.
- Join design methodology innovation for application.
Requirements:
- Bachelor degree or above, major in Microelectronics, electronic engineering, computer science or relevant disciplines.
- 5+ years’ experience on design or verification with Verilog/SV/VHDL.
- Understand SoC digital design and verification flow.
- Excellent problem analyzing/solving skills. Good collaboration skillset to support global projects. Hard working and team player.
- Good knowledge in C language, Verilog/VHDL/System Verilog.
- Nice to have knowledge of script language (ex. Perl/TCL/Python).
- Nice to have know-how of ARM or AMBA system.
03
MSIP Digital Design Engineer
Location: Tianjin
(上下滑动启阅)
Responsibilities:
- Work with analog designer and system architecture to define the digital part for MSIP/ sub-system, including the functionality and algorithm.
- Implement RTL design with high quality in gate count reduction, DFT coverage and timing closure.
- Implement digital part verification and IP level mixed signal verification.
- Work with analog designer on MSIP view generation and documentation delivery.
- Support SoC level integration / verification / silicon validation.
Requirements:
- Master degree, major in micro-electronics, electronic engineering or relevant disciplines.
- 0~2 years’ working experience.
- Good knowledge in Verilog, VHDL, System Verilog, System C or E, and script language.
- Familiar with Unix/Linux system and EDA tool from Cadence, Synopsis, Mentor for digital and analog development.
- Experience with one or more of the following is a plus: power management, 8bit, 16bit or 32bit Micro-controller, ARM or AHB bus system, script languages.
- Basic knowledge of analog and mix-signal design and simulation is a plus.
- Good communication skills and teamwork for global projects support.
04
Sr. Digital IP Design Engineer
Location: Suzhou
(上下滑动启阅)
Responsibilities:
- Develop RTL for digital IPs or subsystems based on architectural requirements.
- Build testbench, create tests to verify digital IPs, and then report coverage of verification.
- Develop functional timing constraints for IPs.
- Run IP check flows of Lint, CDC/RDC, DFT, Synthesis, etc.
Requirements:
- Master’s degree in Microelectronics, Electronics, Electrical Engineering, Computer Science or relevant disciplines.
- 5+ years of work experience in RTL Design and Verification.
- Mandatory Tool Exposure: NCSim/VCS, Spyglass or Questa LINT/CDC.
- Mandatory Skills: Verilog/System Verilog.
- Automation Tools: Shell, TCL, Perl, Python, etc.
05
Principal Digital IP Design Engineer
Location: Suzhou
(上下滑动启阅)
Responsibilities:
- Develop RTL for digital IPs or subsystems based on architectural requirements.
- Build testbench, create tests to verify digital IPs, and then report coverage of verification.
- Develop functional timing constraints for IPs.
- Run IP check flows of Lint, CDC/RDC, DFT, Synthesis, etc.
Requirements:
- Master’s degree in Microelectronics, Electronics, Electrical Engineering, Computer Science or relevant disciplines.
- 6+ years of work experience in RTL Design and Verification.
- Mandatory Tool Exposure: NCSim/VCS, Spyglass or Questa LINT/CDC.
- Mandatory Skills: Verilog/System Verilog.
- Knowledge on USB or multimedia(display, graphic, video) is preferred.
06
Mixed Signal Design Engineer
Location: Tianjin
(上下滑动启阅)
Responsibilities:
- Design, implement and verify analog/mixed-signal IP.
- Provide technical guidance to layout, application, and validation engineers.
- Create thorough review documentation and follow established design flow.
- Interface with digital & SOC team to define architecture.
- Evaluate and validate designs in the lab and identify any deviations from requirements and implement corrective actions.
- Support production team to develop test plan and failure analysis for final products.
- prefer to be familiar with analog IP design, including but not limited PLL/ADC/PMIC…
Requirements:
- Master's degree over 1year’s experience , or Bachelor's degree over 3years’ experience in Electrical Engineering.
- Thorough understanding of analog and mixed signal design.
- Strong skills in designing various analog/mixed-signal blocks.
- Familiar with design/simulation/verification tools.
- Lab and test equipment skills for debug, characterization, and validation of designs.
- Good English written and oral communication skill.
- Enthusiastic, creative, motivated and result-oriented.
07
Principal Mixed Signal Design Engineer
Location: Suzhou
(上下滑动启阅)
Responsibilities:
- Responsible for analog / mixed-signal IP architecture definition and IP design for ARM-based MCU/MPU product development.
- Independent IP schematic design / analog & mix-signal simulation/ layout design / IP view generation / technical documentation.
- Work with SoC / Backend team on IP integration.
- Work with test/validation/qualification team on IP validation, characterizations and failure analysis.
Requirements:
- Master degree, major in micro-electronics, electronic engineering or relevant disciplines.
- 8+ years’ analog / mixed-signal IP design experience.
- Familiar with analog/mixed-signal IP design, simulation, integration and validation flow with industrial standard EDA tools and test equipment.
- Familiar with design EDA tool: Cadence Virtuoso, Hspice/Spectre, Calibre, Matlab, QRC , etc.
- Experience in high performance PMU/ DCDC / Data-Conversion / Clocking / OPAMP design is a plus.
- Good communication skills and teamwork for global projects support.
08
Backend Design Engineer
Location: Suzhou
(上下滑动启阅)
Responsibilities:
- Work closely with SoC team (architects, logic designers, etc) for chip/block level physical designs.
- Responsible for chip and block level low power definition, RTL synthesis, logic/power equivalent check, clock tree synthesis, P&R, STA/timing noise closure, etc.
- Responsible for die size estimation, floor-plan and power/IR analysis, DRC/LVS, etc.
Requirements:
- Master or bachelor degree, majoring in microelectronics, electronic engineering , computer science or relevant disciplines.
- 0~2 years’ working experience.
- Good knowledge in SoC backend design and EDA tools.
- Script coding ability of C/C++, Perl/TCL, in Linux/Unix environment.
- Excellent communication skills and collaboration spirit.
- Knowledge of SoC frontend and DFT is preferred.
09
Sr. Backend Design Engineer
Location: Suzhou
(上下滑动启阅)
Responsibilities:
- Work closely with SoC team (architects, logic designers, etc) for chip/block level physical designs.
- Responsible for chip and block level low power definition, RTL synthesis, logic/power equivalent check, clock tree synthesis, P&R, STA/timing noise closure, etc.
- Responsible for die size estimation, floor-plan and power/IR analysis, DRC/LVS, etc.
Requirements:
- Master or bachelor degree, majoring in microelectronics, electronic engineering , computer science or relevant disciplines.
- Good knowledge and 3+ years’ experience in SoC backend design and EDA tools.
- Script coding ability of C/C++, Perl/TCL, in Linux/Unix environment.
- Excellent communication skills and collaboration spirit.
- Knowledge of SoC frontend and DFT is preferred.
10
SoC Implementation Engineer
Location: Tianjin
(上下滑动启阅)
Responsibilities:
- High performance Micro Processor Synthesis and Static Timing Analysis.
- Floorplan, Place&Route and physical verification.
- Power integrity analysis.
Requirements:
- Master Degree, major in Micro Electronics or other relevant disciplines.
- Have 0-2 years' related working experience.
- Good knowledge in semiconductor process technology and digital circuit.
- Familiar with SoC implementation methodology.
- Design experience in production tape-outs.
- Good listen, write and spoken English.
- Enthusiastic, creative, motivated and collaborative.
11
Sr. SoC Implementation Engineer
Location: Tianjin
(上下滑动启阅)
Responsibilities:
- Capability to accurately and efficiently work on multiple projects.
- Coordinate project plan execution and collaborates with various functional levels, including Marketing, Procurement, Product Engineering, Planning, Program Management & Vendors to meet schedule and budget targets.
- Obtain quotes from vendors and manage project purchase orders through production release.
- Pursue and support cost reduction activities to achieve established company goals.
- Ability to proactively identify and resolve engineering and manufacturing related issues and have a thorough understanding of PCB & PCBA manufacturing.
- Interacts with Contract Manufacturers (CM) to resolve component procurement issues, and review the production cost.
- Address vendor and CM issues including delivery, quality, and costs through corrective actions.
- Participate in peer reviews of program management and contract manufacturing to improve hardware development process across the Board Solutions Group.
- Possess a detailed knowledge of an Agile & ERP system.
- Review and approve Engineering Change Orders (ECO) applicable to products.
- Provide technical support via direct communication to internal customers & contract manufacturer.
- Schedule first article acceptance by stakeholders including Out of Box Experience (OOBE) and System Validation Test (SVT) when required.
- Work cross functionally to ensure the resolution of problems and actions as needed.
Requirements:
- Bachelor’s degree or above, major in electronics, product & industrial design, or related field.
- Minimum of 5 years of experiences in hardware board design or equivalent working experience in a design/manufacturing environment.
- Understand system-level design including mechanical, thermal, PCBA, cabling, PSU, firmware, etc.
- Understand the manufacturing process and quality requirements. Understand the DFx process.
- Solid high-speed digital signal design and test experience is required.
- Solid understanding of electronics components are required.
- Understand regulatory requirements and experience with compliance tests like FCC/CE.
- Master Cadence tools including Allegro and OrCAD.
- Good technical and analytical skills with the ability to perform electronic system troubleshooting and debug effectively.
- Experience in Ethernet switch, router, wireless charging, embedded systems, power meter, RF and wireless, Touchpad/Touch-screen system development will be an extreme advantage.
- Knowledge in CPLD design, micro-Controller programming, Linux programming will be an advantage.
- Excellent interpersonal and communication skills, good teamwork adaptability, good oral and written English skills, self-motivated.
# DFT, Verification, Validation #
01
SoC DFT Engineer
Location: Suzhou
(上下滑动启阅)
Responsibilities:
- Setup and maintain DFT flow, familiar with script language.
- Be responsible for definition and implementation different schemes of DFT aspects: including scan/MBIST/JTAG insertion, ATPG generation, test patterns generation.
Requirements:
- Bachelor or master degree, majoring in microelectronics, electronic engineering , computer science or relevant disciplines.
- Minimum 3 years’ related working experience.
- Proficiency in whole DFT architecture definition.
- Experience RTL/netlist simulation, good debug capability , familiar with Verilog.
- Experience with ATE on-line debugging and DFT diagnosis.
- Experience with Post-silicon DPPM improvement , coverage hole analysis.
02
SoC Design & Verification Engineer
Location: Shanghai
(上下滑动启阅)
Responsibilities:
- Block level verification based on System Verilog & UVM methodology for the complex new IP design and SoC fabric verification.
- Responsible for verification plan quality, verification result/design target cross-check, test case development to have better coverage and verification quality.
- Co-work with functional verification team to ensure the complex SoC verification functional coverage and quality.
Requirements:
- Bachelor or master’s degree in Microelectronics, Electronics, Electronic Engineering, Computer Science or relevant disciplines.
- 5+ years’ related working experience.
- Good knowledge and experience in C/C++/Verilog/System Verilog/UVM programming languages, familiar with IC simulation&debug flow and tools,testbench build, unix/linux environment, tcl/perl script etc.
- Solid UVM experiences are required.
- Good Knowledge of computer architecture, especially ARM CPU(Cortex A/M series), bus protocols(APB/AHB/AXI), verification experience of ARM-based SoC is a plus.
03
Design Emulation & Validation Engineer
Location: Suzhou
(上下滑动启阅)
Responsibilities:
- Define the Emulation(FPGA/Zebu/Veloce) development plan according to the requirement from the different functional team.
- Build and delivery Emulation(FPGA/Zebu/Veloce) platform to other functional team before silicon coming back.
- Create and execute Pre-Si and Post-Si validation plan based on the technical specification.
- Co-work with global functional team to investigate and identify the digital or analog design issues.
Requirements:
- Bachelor degree or above, major in electrical/computer engineering or relevant disciplines.
- Have 0-2 years' related working experience.
- Familiar with Xilinx device structure & synplicity tools (synplify_premier, identify, certify) & Xilinx PAR tools.
- Experienced in FPGA design & simulation environment setup.
- Good understanding of the FPGA timing, FPGA clocking.
- Must be proficient in Verilog HDL.
- Familiar with logic simulators and debug tools (VCS, NCSIM, Verdi and etc.).
- Working knowledge in C/C++, Makefile.
- Experience in ARM M0+, M4 and M7 based MCU is a strong plus.
- Experience in Keil, IAR or CodeWarrior debugger tool is a strong plus.
- Fluent English (both written and spoken) and excellent communication skills.
- Ability to write professional and technical reports and procedures.
# Others #
01
Information Developer
Location: Suzhou / Tianjin
(上下滑动启阅)
Responsibilities:
- Work closely with engineering to scope, create, edit, and publish hardware documentation necessary for world-wide customers to design systems using NXP processors.
- Collect and integrate content originating from SoC and IP Design, systems and software engineers.
- Analyze specifications, register definitions, and functional descriptions for accuracy, completeness, and clarity.
- Technical editing duties include improving information mapping of content, ensuring adherence to style and language standards, and coordinating with functional teams for review, approval, and release of documents.
- Follow standardized processes and workflows in a cross-functional team environment.
Requirements:
- Engineering, Computer Science degree OR Technical English, Master of Translation and Interpreting (MTI) degree with strong technical background; must have industry experience in the generation of complex technical documents in an engineering environment.
- 3+ years of technical writing and editing experience preferably in the semiconductor domain, desirable.
- Strong understanding of DITA/XML fundamentals, structured writing, and single-sourcing principles.
- Experience in using documentation authoring tools, such as XML editors (oXygen, Doxygen, Notepad++), FrameMaker, Microsoft Word, and graphics tools, such as Inkscape or Adobe Illustrator.
- Must be process oriented and be able to communicate information development flows/guidelines to cross-functional teams.
- Interested in growing technical skills in both hardware and software.
- Enjoys working in a fast-paced, interrupt-driven environment with frequent internal-customer interaction.
- Good organizational and time management skills.
- Excellent command of the English language and strong verbal and written communication skills.
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